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Ordering number : ENA0991
LV8071LP
Overview
Bi-CMOS IC
Piezoelectric Actuator Driver IC
The LV8071LP is a piezoelectric autofocus actuator driver IC for use in cell phone cameras. It internally generates drive waveforms, which reduces DSP load and makes it possible to control piezoelectric actuators by simple control signals.
Features
The actuator using the piezoelectric device is driven by the external CLK input and simple control signal. * The 39MHz (CLK1 pin input) CLK input is divided into quarters internally to generate the 9.75MHz input. The operation time is generated using this as a base CLK to ensure the output appropriate for piezoelectric drive. The CLK2 input of 9.75MHz is input to be used, as it is, for the base CLK either. * IC start/stop is controlled by the EN input. Initialization is made according to the built-in sequence at startup. * The actuator drive time is determined by inputting the pulse to the DRIVE pin. * To recognize operation/stop of the actuator, the BUSY signal is output while the OUT pin performs any output.
Specifications
Maximum Ratings at Ta = 25C, GND = 0V
Parameter Supply voltage Output current Input signal voltage Allowable loss Operating temperature range Storage temperature Symbol VCC max IO max VIN max Pd Topr Tstg Mounted on a specified board* Conditions Ratings -0.5 to 6.0 300 -0.5 to VCC+0.5 700 -20 to +85 -55 to +150 Unit V mA V mW C C
Note *: Mounted on a specified board: 40.0mmx50.0mmx0.8mm, glass epoxy board
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. www..com Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
D1907 TI IM 20060124-S00004 No.A0991-1/6
LV8071LP
Allowable Operating Condtions at GND = 0V
Parameter Supply voltage Input signal voltage Input CLK1 frequency Input CLK2 frequency DRIVE "H" minimum pulse width DRIVE "L" minimum pulse width Maximum operation cycle frequency Symbol VCC VIN FCLK1 FCLK2 DH min DL min Ct max CLK1 pin CLK2 pin 1clk=1/4CLK1=CLK2 1clk=1/4CLK1=CLK2 1 cycle = 87clk Conditions Ratings 2.5 to 3.3 0 to VCC 39 9.75 96 96 140 cycles x 170 Unit V V MHz MHz clk clk times
Electrical Characteristics at Ta = 25C, VCC = 2.8V, GND=0V, unless otherwise specified.
Parameter Current drain at standby 0 Current drain during operation "H" level input voltage "L" level input voltage Output block upper-side ON resistance Output block lower-side ON resistance Turn-ON time Turn-OFF time Symbol ICC0 ICC1 VIH VIL RonP RonN TPLH TPHL at no load * at no load * Conditions min No CLK input At CLK1=39MHz 2.5V VCC 5.5V 2.5V VCC 5.5V 0.8 x VCC 0 1.0 1.0 0.4 Ratings typ max 1.0 0.7 VCC 0.1 x VCC 1.5 1.5 0.2 0.2 A mA V V s s Unit
Note: The time for 1090% at rise and 9010% at fall is specified.
Package Dimensions
unit : mm (typ) 3318
TOP VIEW 2.6 SIDE VIEW BOTTOM VIEW (0.125)
(0.13)
(C0.116)
2.6
0.4
2 LASER MARKED INDEX 0.5 (0.55)
1
SIDE VIEW
(0.035)
0.25
0.8
SANYO : VCT16(2.6X2.6)
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16
No.A0991-2/6
LV8071LP
Pin Assignment
M/I 16 DRIVE 1 EN 15 VCC 14 (NC)
0.8
Pd max - Ta
Mounted on a specified board: 40.0mmx50.0mmx0.8mm, glass epoxy 4-layer substrate (2S2P)
Allowable Power Dissipation, Pd max - W
13 12 OUT1
0.7 0.6 0.5 0.4
TEST1
2
11 (NC)
LV8071LP
TEST2 3 10 RFG
0.36 0.3 0.2 0.1 0 -20
CLK1
4 5 CLK2 6 BUSY 7 GND 8 OUT2
9
(NC)
0
20
40
60
80
100 ILV00256
Ambient Temperature, Ta- C
Top view
Block Diagram
VCC
CLK1 CLK2 EN M/I DRIVE
Quarterdividing circuit
OUT1
CLK select Actuator drive waveform generated
GATE A GATE B busy
OUT2 RFG
BUSY
TEST1
TEST2
GND
Resistance to be provided to the RFG pin In LV8071LP, insertion of the resistor between RFG and GND pins enables suppression of the inrush current to the piezoelectric element. Since the resistance value exerts influence on the actuator operation, determine the constant within the 0 to 3.3 range while checking the operation.
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No.A0991-3/6
LV8071LP
Description of the Operation
* CLK1 and CLK2 inputs CLK1 incorporates the quarter-dividing circuit. To input 39MHz directly, input it directly to the CLK1 pin. When the dividing circuit is provided externally, input 9.75MHz to the CLK2 pin. Short-circuit the unused CLK pin to GND. * 1 cycle: One cycle (8.923s for CLK1=39MHz or CLK2=9.75MHz) of OUT waveform operation is used as one unit of output operation. The drive waveform appropriate to piezoelectric drive as shown below is generated in IC. (1clk=1/4CLK1=1CLK2)
87clk = 1 cycle 23clk
4clk
34clk
* EN input: L input causes the IC functions to stop to suppress the current drain in the standby state. H input causes IC to start. After initialization according to the start sequence, the DRIVE pin is ready to accept the input. * Initialization: Internal sequence to move the actuator to the initial position at start of IC. After the operation of 140 cycles x 170 times in the direction, the standby time of 140 cycles x 4 times is secured. Then, 140 cycles x 2 times of return operation is made in the macro direction. * DRIVE input: Operation time setting pin. The pin performs 140 cycles of operation per pulse at pulse input. To prevent noise-induced error, the input with the pulse H/L width of 96clk (9.85s when CLK = 39MHz) respectively is not accepted. * M/I input: Actuator operation direction setting pin. Actuator is set in the macro direction at the input H and in the direction at the input of L. The actuator stops operation if M/I is changed over even when it is operating with the DRIVE pulse. * TEST1/2 Setting pin for IC inspection. Short-circuit this pin with GND during actual use. * BUSY output: The signal output pin, which outputs "H=VCC voltage while the actuator is operating and "L" when the actuator is stopped.
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No.A0991-4/6
LV8071LP
Timing Chart (For CLK1=39MHz)
EN direction logic select M/I DRIVE 8.923s GATE A GATE B Operating in the direction Operation start at DRIVE input 280 cycles = 5.00ms BUSY Returns to "H" with "EN=L" even during operation Operating in the macro direction Operation for 2 pulses = 280 cycles Operation stop with EN input at "L" Macro direction logic select
BUSY output "H" only during operation
Enlarged view of gate signal sequence
Operating in the direction
8.923s 2.359s 2.359s
GATE A 410ns GATE B 3.487s 3.487s
Operating in the macro direction 410ns GATE A 3.487s GATE B 2.359s
8.923s
3.487s
2.359s
Initialization sequence at startup
Start with EN=H. Initialization sequence starts. EN 8.923s GATE A GATE B Operating in the direction Standby state 140 cycles x 4 = 5.00ms Initialization about 220ms Operating in the macro direction 140 cycles x 2 = 2.50ms
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140 cycles x 170 = 212.3ms
BUSY "H" during initialization even in the standby state BUSY output "L" at end of initialization BUSY output "H" during initialization
No.A0991-5/6
LV8071LP
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This catalog provides information as of December, 2007. Specifications and information herein are subject to change without notice.
PS No.A0991-6/6

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